This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports different block sizes for the\r\ncomputation of the DCT, that is, 4 Ã?â?? 4 up to 32 Ã?â?? 32, the design of a flexible architecture to support them helps reducing the area\r\noverhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for\r\nlarge video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices\r\nin order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed\r\narchitecture sustains real-time processing of 1080P HD video codec running at 150 MHz.
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